Delay lock-loops (DLLs) have been widely used to generate on-chip clocks in microprocessors, memory interfaces, and communication circuits. DLLs include a delay block having an input to receive a reference signal and an output to provide a delayed version of the reference signal. The delay block often includes a series of delay elements, which may be individually controlled to adjust the cumulative delay through the delay block. DLLs further include a phase detector coupled to the input and the output of the delay block to detect a phase error between the reference signal and the delayed version of the reference signal and to adjust the delays in a series of delay elements so that cumulative delay through the series of delay elements is equal to a known reference delay.